Workshops & Tutorials

Modelling and Analysis Techniques Address Network Performance and Signal Integrity
TUESDAY 18th NOVEMBER
2.30pm – 4.30pm
Rm 103A Ground Floor
NO CHARGE IF YOU BOOK NOW (as part of your pre-registration)
$25 USD per person if booked on the day

One key area of challenge in integrating systems is in the network infrastructure delivering the communication capability. Many network technologies are available, and are often adopted for tasks in innovative ways that stress the capacity and performance to the limits. To be able to design a network in a modeled form, and analyze it's characteristics in extremes of operating conditions, can help reveal problems - and optimize bandwidth and safety margins - early enough in the design flow to avoid expensive rework and major production delays.

The IEEE Standard 1076.1 for the VHDL-AMS language provides hardware modeling capabilities that are well suited for network signal integrity analysis. This includes modeling the analog, digital and mixed-signal aspects of the transceivers, as well as the behavior of twisted-pair transmission lines, connectors and other components of the network Physical Layer.

This presentation will show various modeling approaches applicable to the key hardware components of a network, using as the primary example a CAN bus configuration.
It will also provide examples of simulation-based techniques for network signal integrity design, including:
• Analyzing static and dynamic features of transceivers, lines and other components
• Examining termination strategies
• Characterizing data delay vs. intermediate-node stub-length
• Assessing Electrostatic Discharge (ESD) protection capability of Transient Voltage Suppression components

The session demonstrates a wide range of modeling, simulation and analysis capabilities that are applicable to CAN Bus Physical Layer design and can also be applied to other networking implementations and protocols.

The VHDL-AMS hardware description language provides a solid foundation for building models at the right level of detail for design verification, parametric trade-off analysis, and EMI/ESD assessment. This enables higher quality results in network designs, with greater utilization and performance, and reduced risks of in-service problems.

About the Speaker:

Rick Pier & David Landoll
Mentor Graphics